CC2530 – IO端口

注明

  • 本文摘译自TI(德州仪器)公司的《CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee® Applications User’s Guide》。
  • 文件号:SWRU191F。
  • 所有版权归TI(德州仪器)公司所有。
  • 本文章节序号与原文相同。

7. 输入/输出端口

数字I/O针脚共有21个,可以设定为通用数字I/O或者是连接到ADC、定时器、USART等外围设备信号的外围设备I/O。这些I/O端口的使用均可由用户通过对寄存器的设置实现。
I/O端口主要有以下几个特征:

  • 共21个数字I/O针脚
  • 通用数字I/O或外围设备I/O模式
  • 上拉/下拉(高/低电平)输入方式
  • 外部中断功能

所有I/O针脚都有外部中断功能,因此外部设备可以在必要时产生中断。这一特征也可以用于将本芯片从睡眠模式中唤醒(PM1,PM2,PM3电源模式)。

目录

  • 7.1       未使用的I/O针脚
  • 7.2       低I/O电压
  • 7.3       通用I/O
  • 7.4       通用I/O中断
  • 7.5       通用I/O DMA
  • 7.6       外围设备I/O
  • 7.7       调试接口
  • 7.8       32-kHz XOSC输入
  • 7.9       无线电测试输出信号
  • 7.10     掉电信号MUX(PMUX)
  • 7.11     I/O寄存器

7.1 未使用的I/O针脚

未使用的I/O针脚应该进行级别设定且不能悬空。一个解决办法是使其处于未连接状态并将其设置为通用I/O、上拉电阻输入模式。该状态也是所有针脚重置时、重置后的状态(除了P1_0和P1_1,这两个针脚没有上拉/下拉功能)。除此之外,未使用的I/O针脚可以设置为通用I/O输出,但不管是作为输入还是输出,这些针脚都不能直接接到VDD或GND以防止过度消耗电量。

7.2 低I/O电压

在用数字I/O提供电压的应用程序里,DVDD1和DVDD2电压低于2.6V,PICTL.PADSC寄存器位应设置为1以使其具有设备数据手册中“直流特性表”给出的直流输出特性(详见原文附录C)。

7.3 通用I/O

当被作为通用I/O使用时,所有针脚用三个8位端口寄存器表示,分别是P0,P1和P2。P0和P1是完全8位端口,P2仅5位是有效针脚位。所有端口都是通过P0,P1,P2三个SFR寄存器进行位寻址和字节寻址的。每个端口针脚都可单独设置成通用I/O或外围设备I/O。

出了高驱动输出针脚P1_0和P1_1的输出能力可达20mA外,其他针脚的最大输出能力均是4mA。

PxSEL(x从0到2)寄存器用来设置每个端口上的针脚是作为通用I/O还是外围设备I/O。默认情况下,重置之后所有数字I/O针脚都重置为通用I/O。

PxDIR(x从0到2)寄存器用来设置每个端口上的针脚的输入输出方向,当某进制位上数值为1时表明该位对应的针脚为输出,为0时为输入。

对P0,P1和P2端口寄存器进行读取操作时,无论输入针脚定义为什么,都会返回其逻辑值。但当执行“读取-修改-写回”指令时例外,这些指令包括:ANL,ORL,XRL,JBC,CPL,INC,DEC,DJNZ,MOV,CLR,SETS。对端口寄存器进行操作时,以下操作是可靠的:目标地址是P0,P1,P2寄存器上单独的位;将寄存器的值(而非针脚值)读取,修改后写回端口寄存器。

设置为输入方向时,通用I/O端口针脚可设置为上拉,下拉或三态操作模式。重置之后输入端默认为上拉输入。若要取消某个输入端的上拉,下拉功能,需将PxINP相应二进制位的值设为1。P1_0和P1_1两个I/O端口针脚没有上拉和下拉功能。需要注意的是设置成外围设备I/O信号的针脚也没有上拉和下拉功能,即使外围设备的功能是输入类型的。在PM1,PM2,PM3电源模式中,I/O针脚将保留之前的I/O模式和输出值(若可用)。

7.4 通用I/O中断

General-purpose I/O pins configured as inputs can be used to generate interrupts. The interrupts can be configured to trigger on either a rising or falling edge of the external signal. Each of the P0, P1, and P2 ports has port interrupt-enable bits common for all bits within the port located in the IEN1–IEN2 registers as follows:

  • IEN1.P0IE: P0 interrupt enable
  • IEN2.P1IE: P1 interrupt enable
  • IEN2.P2IE: P2 interrupt enable

In addition to these common interrupt enables, the bits within each port have individual interrupt enables located in SFR registers P0IEN, P1IEN, and P2IEN. Even I/O pins configured as peripheral I/O or general-purpose outputs have interupts generated when enabled.

When an interrupt condition occurs on one of the I/O pins, the interrupt status flag in the corresponding P0–P2 interrupt flag register, P0IFG, P1IFG, or P2IFG, is set to 1. The interrupt status flag is set regardless of whether the pin has its interrupt enable set. When an interrupt is serviced, the interrupt status flag is cleared by writing a 0 to that flag. This flag must be cleared prior to clearing the CPU port interrupt flag (PxIF). This is illustrated in Figure 2-4: There is an edge detect between the input line and PxIFG, but no edge detect or one-shot between PxIFG and PxINT. The practical impact of this is what is written in Section 2.5.1

The SFR registers used for interrupts are described later in this section. The registers are summarized as follows:

  • P0IEN: P0 interrupt enables
  • P1IEN: P1 interrupt enables
  • P2IEN: P2 interrupt enables
  • PICTL: P0, P1, and P2 edge configuration
  • P0IFG: P0 interrupt flags
  • P1IFG: P1 interrupt flags
  • P2IFG: P2 interrupt flags

7.5 通用I/O DMA

定义为通用I/O针脚使用时,P0和P1端口各自关联一个DMA触发器,分别是IOC_0和IOC_1(详见原文表8-1)。

当P0端口上的针脚发生中断时,IOC_0将被激活,IOC_1同理。

7.6 外围设备I/O

本节介绍如何将数字I/O设置为外围设备I/O。每个外围设备单元都可以通过数字I/O针脚接入外部系统,下面介绍了如何进行外围设备I/O配置。

对于USART和定时器I/O,当数字I/O针脚上的信号是由外围设备输出时,需将PxSEL寄存器响应位置1。对于从数字I/O针脚输入信号的外围设备则无需进行PxSEL设置。诸如PxSEL|=(1<<x)的操作将会覆盖对应针脚上的上拉/下拉态(即切换到了三态模式),所以要开启某针脚的上拉/下拉功能时,应该将相应PxSEL寄存器的相应位置0。

需要注意的是,外围设备单元一般都为自身分配了两个备选I/O针脚位(详见原文表7-1)。如果当前外围设备I/O映射存在冲突(重复)可以通过设置外围设备单元的调用优先级解决(通过P2SEL.PRIxP1和P2DIR.PRIP0两个位)。所有不会引起冲突的映射组合都可以使用。

此外,外围设备在未使用相应I/O口时也会处于占用状态,其他外围设备要对其进行使用必须要有更高的优先级(除了关闭流控且运行在UART模式下的USART的RTS/CTS针脚,以及处于SPI主模式下的USART的SSN针脚)。

同时,如果某外围设备设置有输入I/O针脚,则该针脚会忽略PxINP相应位的设置,这可能会影响外围设备单元的状态。例如当UART的RX针脚在使用前处于活动状态时,应该先清除UART状态再使用。

  • 7.6.1 Timer 1

PERCFG.T1CFG selects whether to use alternative 1 or alternative 2 locations.

In Table 7-1, the Timer 1 signals are shown as the following:

  • 0: Channel 0 capture or compare pin
  • 1: Channel 1 capture or compare pin
  • 2: Channel 2 capture or compare pin
  • 3: Channel 3 capture or compare pin
  • 4: Channel 4 capture or compare pin

P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to Port 0. When set to 10, Timer 1 channels 0–1 have precedence, and when set to 11, Timer 1 channels 2–3 have precedence. To have all Timer 1 channels visible in the alternative 1 location, move both USART 0 and USART 1 to the alternative 2 location.

P2SEL.PRI1P1 and P2SEL.PRI0P1 select the order of precedence when assigning several peripherals to Port 1. The Timer 1 channels have precedence when the former is set low and the latter is set high.

  • 7.6.2 Timer 3

PERCFG.T3CFG selects whether to use alternative 1 or alternative 2 locations.

In Table 7-1, the Timer 3 signals are shown as the following:

  • 0: Channel 0 capture or compare pin
  • 1: Channel 1 capture or compare pin

P2SEL.PRI2P1 and P2SEL.PRI3P1 select the order of precedence when assigning several peripherals to Port 1. The Timer 3 channels have precedence when both bits are set high. If P2SEL.PRI2P1 is set high and P2SEL.PRI3P1 is set low, the Timer 3 channels have precedence over USART 1, but USART 0 has precedence over the Timer 3 channels as well as over USART 1.

  • 7.6.3 Timer 4

PERCFG.T4CFG selects whether to use alternative 1 or alternative 2 locations.

In Table 7-1, the Timer 4 signals are shown as the following:

  • 0: Channel 0 capture or compare pin
  • 1: Channel 1 capture or compare pin

P2SEL.PRI1P1 selects the order of precedence when assigning several peripherals to Port 1. The Timer 4 channels have precedence when the bit is set.

  • 7.6.4 USART 0

The SFR register bit PERCFG.U0CFG selects whether to use alternative 1 or alternative 2 locations.

In Table 7-1, the USART 0 signals are shown as follows:

UART:

  • RX: RXDATA
  • TX: TXDATA
  • RT: RTS
  • CT: CTS

SPI:

  • MI: MISO
  • MO: MOSI
  • C: SCK
  • SS: SSN

P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to Port 0. When set to 00, USART 0 has precedence. Note that if UART mode is selected and hardware flow control is disabled, USART 1 or Timer 1 has precedence to use ports P0.4 and P0.5.

P2SEL.PRI3P1 and P2SEL.PRI0P1 select the order of precedence when assigning several peripherals to Port 1. USART 0 has precedence when both are set to 0. Note that if UART mode is selected and hardware flow control is disabled, Timer 1 or Timer 3 has precedence to use ports P1.2 and P1.3.

  • 7.6.5 USART 1

The SFR register bit PERCFG.U1CFG selects whether to use alternative 1 or alternative 2 locations.

In Table 7-1, the USART 1 signals are shown as follows:

UART:

  • RX: RXDATA
  • TX: TXDATA
  • RT: RTS
  • CT: CTS

SPI:

  • MI: MISO
  • MO: MOSI
  • C: SCK
  • SS: SSN

P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to Port 0. When set to 01, USART 1 has precedence. Note that if UART mode is selected and hardware flow control is disabled, USART 0 or Timer 1 has precedence to use ports P0.2 and P0.3.

P2SEL.PRI3P1 and P2SEL.PRI2P1 select the order of precedence when assigning several peripherals to Port 1. USART 1 has precedence when the former is set to 1 and the latter is set to 0. Note that if UART mode is selected and hardware flow control is disabled, USART 0 or Timer 3 has precedence to use ports P1.4 and P1.5.

  • 7.6.6 ADC

在原文表7-1中,ADC信号表示如下:

  • A0:ADC输入0
  • A1:ADC输入1
  • A2:ADC输入2
  • A3:ADC输入3
  • A4:ADC输入4
  • A5:ADC输入5
  • A6:ADC输入6
  • A7:ADC输入7
  • T:ADC外部触发针脚

ADC最多可使用8个ADC输入,使用时P0端口上的针脚必须设置为ADC输入。设置为输入的方法是将APCFG寄存器相应位置1。此寄存器默认值是将P0端口针脚作为非ADC输入,即数字输入I/O。

对APCFG寄存器的设置将覆盖P0SEL中的设置。

可以将通用I/O口P2_0设置为ADC的外部触发。前提是必须将P2_0设置为通用I/O输入模式。

  • 7.6.7 Operational Amplifier and Analog Comparator

When using the operational amplifier and analog comparator, the corresponding Port 0 pins must be configured as ADC inputs (see Table 7-1). To configure a Port 0 pin to be used as an ADC input, the corresponding bit in the APCFG register must be set to 1. The default values in this register select the Port 0 pins as non-ADC input, that is, digital input/outputs.

The settings in the APCFG register override the settings in P0SEL.

7.7 Debug Interface

Ports P2.1 and P2.2 are used for debug data and clock signals, respectively. These are shown as DD (debug data) and DC (debug clock) in Table 7-1. When in debug mode, the debug interface controls the direction of these pins. Pullup and pulldown are disabled on these pins while in debug mode.

7.8 32-kHz XOSC Input

Ports P2.3 and P2.4 can be used to connect an external 32-kHz crystal. These port pins are used by the 32-kHz XOSC when CLKCONCMD.OSC32K is low, regardless of register settings. The port pins are set in analog mode when CLKCONCMD.OSC32K is low.

7.9 Radio Test Output Signals

By using the OBSSELx registers (OBSSEL0–OBSSEL5) the user can output different signals from the RF Core to GPIO pins. These signals can be useful for debugging of low-level protocols or control of external PA, LNA, or switches. The control registers OBSSEL0–OBSSEL5 can be used to override the standard GPIO behavior and output RF Core signals (rfc_obs_sig0, rfc_obs_sig1, and rfc_obs_sig2) on the pins P1[0:5]. For a list of available signals, see the respective RFC_OBS_CTRLx registers in Section 23.15.3 for CC253x or Section 24.1 for CC2540 or Chapter 25 for CC2541.

7.10 Power-Down Signal MUX (PMUX)

The PMUX register can be used to output the 32-kHz clock and/or the digital voltage regulator status.

The selected 32-kHz clock source can be output on one of the P0 pins. The enable bit CKOEN enables the output on P0, and the pin of P0 is selected using the CKOPIN (see the PMUX register description for details). When CKOEN is set, all other configurations for the selected pin are overridden. The clock is output in all power modes; however, in PM3 the clock stops (see PM3 in Chapter 4).

Furthermore, the digital voltage regulator status can be output on one of the P1 pins. When the DREGSTA bit is set, the status of the digital voltage regulator is output. DREGSTAPIN selects the P1 pin (see the PMUX register description for details). When DREGSTA is set, all other configurations for the selected pin are overridden. The selected pin outputs 1 when the 1.8-V on-chip digital voltage regulator is powered up (chip has regulated power). The selected pin outputs 0 when the 1.8-V on-chip digital voltage regulator is powered down, that is, in PM2 and PM3.

7.11 I/O寄存器汇总

  • P0:端口0
  • P1:端口1
  • P2:端口2
  • PERCFG:外围设备控制寄存器
  • APCFG(ADCCFG):模拟外围设备I/O设置
  • P0SEL:端口0功能选择寄存器(通用I/O或者外围设备I/O)
  • P1SEL:端口1功能选择寄存器(通用I/O或者外围设备I/O)
  • P2SEL:端口2功能选择寄存器(通用I/O或者外围设备I/O)
  • P0DIR:端口0的I/O方向寄存器(输入或输出)
  • P1DIR:端口1的I/O方向寄存器(输入或输出)
  • P2DIR:端口2的I/O方向寄存器(输入或输出)
  • P0INP:端口0输入模式寄存器(上拉/下拉或三态)
  • P1INP:端口1输入模式寄存器(上拉/下拉或三态)
  • P2INP:端口2输入模式寄存器(上拉/下拉或三态)
  • P0IFG:端口0中断状态标识寄存器
  • P1IFG:端口1中断状态标识寄存器
  • P2IFG:端口2中断状态标识寄存器
  • PICTL:中断临界寄存器
  • P0IEN:端口0中断屏蔽寄存器
  • P1IEN:端口1中断屏蔽寄存器
  • P2IEN:端口2中断屏蔽寄存器
  • PMUX:关机/休眠信号MUX寄存器
  • OBSSELx:输出控制监测寄存器x